Integrated capacitors may be largely classified into Metal Oxide Semiconductor (MOS) capacitors, Poly-silicon Insulator Poly-silicon (PIP) capacitors, and a Metal Insulator Metal (MIM) capacitors. Integrated capacitors may be realized within a single device. However, to create a capacitor with a large capacity in a small mounting area, two kinds of capacitors may be connected and used as a single device. An example follows.
FIG. 1 is a cross-sectional view illustrating a structure with a PIP capacitor and a MOS capacitor. In FIG. 1, the left of a reference line A is a region (hereinafter, referred to a first region) of the PIP capacitor and the right is a region of the MOS capacitor (hereinafter, referred to as a second region). The capacitor, having a separated structure, includes a diffusion junction region 11 over a substrate 10, an oxide layer 13 over an entire surface of the substrate 10, a high concentration junction region 12 in a portion of the oxide layer 13 of the second region, first polysilicon layer 14 over the oxide layer 13 and spaced apart from each other in the first region and the second region, a nitride layer 15 over the first polysilicon electrode 14 of the first region, a second polysilicon layer 16 over the nitride layer 15, an insulation layer 17, contact plugs 18a, 18b, 18c, and 18d, and a metal electrode 19. Accordingly, two contact plugs 18c and 18d for forming an electrode of the PIP capacitor and two contact plugs 18a and 18b for forming an electrode of the MOS capacitor, i.e., a total of 4 contact plugs, are formed.
FIG. 2 is a cross-sectional view illustrating a mixed structure of a PIP capacitor and a MOS capacitor. Referring to FIG. 2, a capacitor with a mixed structure includes a substrate 20, a diffusion junction region 21, an oxide layer 23, a high concentration junction region 22, a first polysilicon layer 24, a nitride layer 25, a second polysilicon layer 26, an insulation layer 27, contact plugs 28a, 28b, and 28c, and a metal electrode 29.
A difference between the capacitor of a mixed structure and the capacitor of a separated structure is as follows. First, the first polysilicon layer 24 is not spaced apart and is formed of a single body. That is, in FIG. 1, the first polysilicon layer 14 may be used as an upper electrode of the MOS capacitor, and the first polysilicon layer 14 may also be used as a lower electrode of the PIP capacitor in the separated structure, but in FIG. 2, these are integrated into the first polysilicon layer 24 in the mixed structure.
Second, as the first polysilicon layer 24 is integrated into one body, the top contact plug 18c of the PIP capacitor and the top contact plug 18b of the MOS capacitor in the separated structure shown in FIG. 1 are integrated into the single contact plug 28b in the mixed structure shown in FIG. 2. Third, the contact plug 28b (i.e., the single contact plug) of the second polysilicon layer 26 and the contact plug 28a of the high concentration junction region 22 used as a terminal of the lower metal layer (i.e., the diffusion junction region 21) of the MOS capacitor are connected to a single electrode 29.
The number of electrodes and contact plugs and a mounting area of a capacitor can be reduced in the mixed structure, compared to the separated structure. However, since the high concentration junction region 22 has a structure of the contact plug 28a in the mixed structure, there are limitations in reducing the number of contact plugs and the size of the high concentration junction region 22.